1. Field of the Invention
The present invention relates to a wafer level package fabrication method, and more particularly, to a wafer level package fabrication method that accommodates miniaturization through reducing product size, performs a bonding process without wafer deformation or damage, and increases freedom in material selection for wafers.
2. Description of the Related Art
In general, electronic devices such as a film bulk acoustic resonator (FBAR) and a surface acoustic wave (SAW) filter are being drastically miniaturized and are required to be highly reliable.
Today, electronic devices are being given increased functions and reduced power consumption, and due to continued industry demands for lighter, smaller devices, FBAR devices widely used in mobile phones, etc. are rapidly proliferating. Thus, chip scale packages (CSP) are gradually declining in popularity, and wafer level packages (WLP) are being pursued from many different perspectives, to realize increased yield and lower fabrication costs. Such WLPs are widely thought to be the greatest factor affecting market competitiveness.
The WLP includes a device wafer having a circuit with a miniature driver, a cap wafer coupled at the top of the device wafer, and a sidewall formed of a bonded metal line that couples the device wafer and cap wafer at perimeters thereof and seals the inner space for the driver from the external environment. The cavity (inner space) is for protecting an electrode pattern within from a harmful external environment or impurities.
Methods for fabricating WLPs are disclosed in U.S. Pat. No. 5,448,014 and Japanese Patent Publication No. 2006-197554, which are included herein in their entirety by reference.
However, in such related art methods for fabricating WLPs, deformation and fissures can occur in the device wafer and cap wafer because vertical stacking via melting fusion of the cap wafer and device wafer is performed through providing a metal bonding material on the respective undersurfaces of the cap wafer and device wafer and then applying a high level of heat ranging from approximately 200° C. to approximately 300° C., and the device wafer and cap wafer are limited to the same material or materials that have similar thermal expansion coefficients because deformation or fissure occurrence in wafers is probable when the device wafer and cap wafer are formed of materials having respectively different thermal expansion coefficients.
Also, because related art methods for fabricating WLPs have complicated processes, there are limitations in increasing yield and reducing product cost to increase price competitiveness.
Also, there is a limitation in reducing package size and furthering miniaturization, due to a requirement for a space to be provided between the device portions and the bonding metal lines, in which connection pads must be provided to electrically connect to external terminals, for inputting/outputting signals.